1. Field of the Invention
Embodiments of the invention relate to an image data processing system. More particularly, embodiments of the invention relate to a dithering system and dithering method which can widely disperse an error generated due to a physical limitation of a data bit expressed by a low gray scale system.
2. Discussion of Related Art
A conventional method of displaying images includes converting an actual image to a digital signal, processing the image, and displaying the processed image via a display. The display outputs an image most representative of the actual image through a series of such processes. Various types of displays may be used to display images such as cathode ray tubes (CRT), thin film transistor liquid crystal displays (TFT-LCD), plasma display panels (PDP), etc.
The number of gray scales that can be expressed in an image is limited. For example, when 8 bits of Red (R), Green (G), and Blue (B) image signals are received from an external graphic source, but the image display can only express 6 bits of R, G, and B image signals, the image display is deficient by 2 bits of data from each R, G, and B image signal. As a result a false contour line in which a clear contour appears on the boundary of a screen or a mach's phenomenon in which a bright or dark line appears may occur. The false contour line and Mach's phenomenon deteriorates image quality requiring the use of dithering technology to correct the image.
A frame rate control (FRC) method may also be used to compensate for false contour lines and Mach's phenomenon. When using the FRC compensation method, a larger number of gray scales is expressed as an average brightness by controlling the gray scale. The FRC method can display a plurality of frames during one frame time in order to express gray scales associated with a frame. Hereinafter, it is assumed that received data comprises 8 bits and a drive integrated circuit can process data comprising 6 bits. A gray scale voltage corresponding to the 6 most significant bits of received 8 bit data is selected and the gray scale of a frame is controlled where the frame is divided into 4 segments having values (00, 01, 10, and 11) to represent the 2 least significant bits. For example, when the received 8 bit data is 11001011, four frames represented by data strings of 110010, 110011, 110011, and 110011 are displayed during one frame period. Accordingly, 8 bits of data can be expressed in 6 bit form.
FIG. 1 is a block diagram illustrating a conventional image display 100 having a timing controller 110, data driver 130, gate driver 140, and liquid crystal panel 150. A dithering system 120 may be installed inside timing controller 110. Timing controller 110 receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock MCLK signal, a data enable signal DE, and image data R, G, and B from an external graphic source (not shown). Timing controller 110 generates a first timing signal based on vertical synchronization signal Vsync and horizontal synchronization signal Hsync which controls the display of image data R, G, and B and outputs image data R, G, and B with the first timing signal to data driver 130. First timing signal includes load signal TP and horizontal synchronization start signal STH.
Timing controller 110 generates a second timing signal based on the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync. The second timing signal controls the display of image data R, G, and B, and the second timing signal is outputted to gate driver 140. The second timing signal includes a gate selection signal CPV, a vertical synchronization start signal STV, and an output enable signal OE. Data driver 130 sequentially provides the R, G, and B image data corresponding to horizontal lines starting from a first horizontal line to source lines in response to the first timing signal. Gate driver 140 sequentially provides a gate voltage to the gate lines in response to the second timing signal. The liquid crystal panel 150 is formed of a plurality of thin film transistors with crossing points of the source and gate lines. When dithering system 120 is installed in timing controller 110, dithering system 120 converts M bit image data R, G, and B received from the external graphic source to N bit image data R′, G′, and B′. The N bit image data R′, G′, and B′ is outputted to data driver 130. Accordingly, dithering system 120 uses M−N bit dither data where the dither data is added to the M bit image data R, G, and B, and the N bit image data R′, G′, and B′ is generated by cutting off the bottom M−N bit.
FIG. 2 illustrates a table for describing a conventional dithering method where 8 bit input data received from an external graphic source may have 0 to 255 gray scales represented in binary number by 00000000 to 11111111. In order to express 8 bit data in 6 bit form, the bottom 2 bits of the 8 bit input data (Least Significant Bits LSB[1:0]) are cut-off. Thus, output data can only have 0 to 63 gray scales. The decrease in the number of gray scales may cause a false contour line or a Mach's phenomenon as described above.
As described above, the FRC method converts received M bit image data to N bit image data to process the M bit image data in N bit data driver where N<M. In other words, the FRC method is used to represent a frame as plural sub-frames by over-sampling the frames. Referring to FIG. 2, the 8 bit input data is over-sampled in order to make 4 segments of 8 bit input data. Then, the dither data is sequentially added to each of the 4 segments of 8 bit input data. The bottom 2 bits are cut-off in order to express the 4 segments of 8 bit input data as 4 sub-frames. The four sub-frames are all outputted to corresponding pixels in the same time as it takes one frame to be outputted.
In the dithering method, input data (00000010) is over-sampled to generate four strings of the input data. Next, dither data (00, 01, 10, 11) having different sizes are sequentially added to each of the over-sampled input data to generate binary values 00000010, 00000011, 00000100, and 00000101. The bottom 2 bits (LSB [1:0]) are then cut-off in order to generate 6 bit data 000000, 000000, 000001, and 000001. The four strings of 6 bit data are each applied to a corresponding pixel of a liquid crystal panel via a data driver. By using the dithering method, an average brightness of the 8 bit input data can be expressed through a plurality of strings of 6 bit output data, thereby improving resolution.
However, an error usually accompanies usage of the dithering method. For example, when input data is 11111100, the maximum value the input data can have by adding the dither data is 11111111. When the input data is 11111101, the maximum value the input data can have by adding the dither data is 100000000. Accordingly, even when the bottom 2 bits of the maximum value are cut-off, an image display cannot process the input data. This phenomenon is called “overflow.” In an image display which receives M bit input data and outputs N bit output data, input data which exceeds (2M−1)−(2M−N−1) cannot be processed using the conventional dithering method. That is, when 8 bit data is converted to 6 bit data using the dithering method, 3 mappings of an output against an input cannot be realized. A look-up table is used in conventional dithering methods in order to form 3 inflection points in the vicinity of 255 by mapping input data exceeding 252 as 252. Alternatively, the dithering method uses a lookup table to disperse an inflection point throughout the entire gray scale value by converting 0 to 255 domains which is a gray scale value where the input data has 0 to 252 domains. However, several logic gates are used to form the lookup table which increases the chip area for the timing controller and requires additional power. This is disadvantageous especially in a portable high definition multiplayer providing high image resolution.